1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, wherein a multi-layered hard mask layer having a stacked structure of nitride film/oxide film/nitride film for formation a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is employed to protect a lower structure such as a gate electrode in a subsequent process without increasing the thickness of the hard mask layer, and to prevent void and patterning problem resulting from large step difference due to the thickness of the hard mask layer.
2. Description of the Prior Art
Developments in techniques for forming a microscopic pattern on a semiconductor substrate have led to an increased use of highly integrated semiconductor devices. Forming microscopic patterns in a semiconductor requires a photoresist film mask which is used commonly in etching and/or ion implantation to have microscopic patterns.
In general, the resolution (R) of a photoresist film pattern is proportional to the light wavelength (λ) and the process variable (k) of a micro exposure device. The resolution, however, is inversely proportional to the numerical aperture (NA) of the light exposure device.
[R=k*λ/NA, R=resolving power, λ=wave of light source, NA=numerical aperture]
Here, one can improve the resolution by decreasing the light wavelength, for example, the resolution of G-line (λ=436 nm) and i-line (λ=365 nm) micro exposure devices are about 0.7 μm and 0.5 μm, respectively. A photoresist film pattern below 0.5 μm typically requires a deep ultraviolet (DUV) light exposure device which generates a small wavelength length, for example, a KrF laser (248 nm) or an ArF laser (193 nm).
Other methods for improving the photoresist pattern resolution include using a phase shift mask as a photo mask; using a contrast enhancement layer (CEL) method to form a thin film to enhance an image contrast on a wafer; using a tri-layer resist (TLR) method having an intermediate layer, such as a spin on glass (SOG) film, between two photoresist films; and using a silylation method to selectively implant a silicon into the upper portion of a photoresist film.
In a highly integrated semiconductor device, the size of a contact hole connecting the upper and lower conductive interconnections and the space between the contact hole and the adjacent interconnection are smaller relative to a less integrated semiconductor device. In addition, the aspect ratio of the contact hole in a highly integrated semiconductor device is typically higher than a less integrated semiconductor device. Thus, a highly integrated semiconductor device having a multi-layer conductive interconnection requires a precise mask alignment during its fabrication process, which reduces the process margin, i.e., acceptable error limit.
In order to maintain a space between contact holes, in conventional processes, masks are formed with consideration to misalignment tolerance, lens distortion in the exposure process, critical dimension variation in the mask formation and photoetching processes, and mask registrations.
A direct etching method, a sidewall spacer forming method or a self aligned contact (SAC) method have been used for the above contact hole formation process.
The direct etching method and the sidewall spacer forming method cannot be used in fabricating a device having a design rule of less than 0.3 μm. As a result, those methods have limits in high integration of a device.
The self aligned contact (SAC) method to overcome some of the disadvantages of lithography processes typically uses a polysilicon, a nitride, or an oxide nitride material as an etching barrier film. Of these, a nitride material is preferably used as an etching barrier film.
FIGS. 1a through 1d are cross-sectional diagrams illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1a, a gate oxide film 12, a conductive layer 14 such as polysilicon layer or tungsten layer, and a hard mask layer consisting of a nitride film are sequentially formed on a semiconductor substrate 10.
Referring to FIG. 1b, a photoresist film pattern (not shown) for patterning a gate electrode is formed on the hard mask layer 16. The hard mask layer 16, the conductive layer 16 and the gate oxide film 12 are sequentially etched using the photoresist film pattern as a mask to form a gate electrode 18 including a hard mask layer 16 pattern. A portion of the hard mask layer 16 is removed in the etching process.
Referring to FIG. 1c, an insulating film spacer 20 is formed on a sidewall of the gate electrode 18 and the hard mask layer 16 pattern. Thereafter, an interlayer insulating film (not shown) is formed on the entire surface of the resulting structure. The interlayer insulating film is then etched to form a landing plug contact hole. Next, a polysilicon layer 22 for a landing plug is formed on the entire surface of the resulting structure.
Referring to FIG. 1d, the polysilicon layer 22 is planarized via a chemical mechanical polishing (CMP) process to form a landing plug 24. A portion of the hard mask layer 16 is again removed by the CMP process.
According to the conventional method, a hard mask layer is damaged during the formation process of the landing plug. This damage leads to an exposure of the gate electrode in a subsequent bitline, a storage electrode or metal contact formation process, resulting in short between wirings. When a mask layer is formed to have a sufficient thickness to overcome the above-described problem, large step difference is generated during the patterning process of the gate electrode. The insulating film formed in the subsequent process will not be able to fill the gap between gate electrodes, thereby generating a void. Moreover, the hard mask layer pattern remaining after a CMP process has poor uniformity resulting in degradation of yield and reliability of a device.